56 use ieee.std_logic_1164.
all;
57 use ieee.numeric_std.
all;
99 signal pltbs : pltbs_t := C_PLTBS_INIT;
114 signal s_slv : std_logic_vector(7 downto 0);
115 signal s_u : unsigned(7 downto 0);
116 signal s_s : unsigned(7 downto 0);
130 constant C_EXPECT_FAIL :
boolean;
131 variable v_checks_cnt :
inout integer;
132 variable v_errors_cnt :
inout integer;
133 signal checks_cnt :
out integer;
134 signal errors_cnt :
out integer
137 v_checks_cnt := v_checks_cnt + 1;
138 if C_EXPECT_FAIL then
139 v_errors_cnt := v_errors_cnt + 1;
141 checks_cnt <= v_checks_cnt;
142 errors_cnt <= v_errors_cnt;
143 end procedure check_cnt;
163 elsif (clk'event and clk = '1') then
167 end process p_clk_cnt;
171 variable pltbv : pltbv_t := C_PLTBV_INIT;
172 variable v_expected_tests_cnt : integer := 0;
173 variable v_expected_skiptests_cnt : integer := 0;
174 variable v_expected_checks_cnt : integer := 0;
175 variable v_expected_errors_cnt : integer := 0;
176 variable v_expected_data : integer;
177 variable v_actual_data : integer;
178 variable f_status : file_open_status;
180 type charfile
is file of character;
181 file binfile : charfile;
183 variable c : character;
184 variable i : integer;
185 variable v_errcnt : integer;
187 variable line_num : integer := 0;
190 print(lf & "<Testing startsim()>");
192 wait until rising_edge(clk);
193 assert (pltbv.test_num = 0) and (pltbs.test_num = 0)
194 report "test_num after startsim() incorrect"
196 print("<Done testing startsim()>");
198 print(lf & "<Testing starttest() with auto-incrementing test_num>");
199 starttest("StartTest1", pltbv, pltbs);
200 v_expected_tests_cnt := v_expected_tests_cnt + 1;
201 wait until rising_edge(clk);
202 assert (pltbv.test_num = 1) and (pltbs.test_num = 1)
203 report "test_num after starttest() incorrect"
205 print("<Done testing starttest() with auto-incrementing test_num()>");
207 print(lf & "<Testing endtest()>");
208 endtest(pltbv, pltbs);
209 print("<Done testing endtest()>");
211 print(lf & "<Testing starttest() with explicit test_num>");
212 starttest(3, "StartTest2", pltbv, pltbs);
213 v_expected_tests_cnt := v_expected_tests_cnt + 1;
214 wait until rising_edge(clk);
215 assert (pltbv.test_num = 3) and (pltbs.test_num = 3)
216 report "test_num after startsim() incorrect"
218 print("<Done testing starttest() with explicit test_num>");
220 print(lf & "<Testing starttest() and is_test_active() for non-skipped test>");
221 starttest(4, "NoSkipTest", pltbv, pltbs);
223 if (is_test_active(pltbv)) then
224 v_expected_tests_cnt := v_expected_tests_cnt + 1;
225 wait until rising_edge(clk);
227 v_expected_skiptests_cnt := v_expected_skiptests_cnt + 1;
228 wait until rising_edge(clk);
230 report "Executing test that should have been skipped"
234 endtest(pltbv, pltbs);
235 print("<Done testing starttest() and is_test_active() for non-skipped test>");
237 print(lf & "<Testing starttest() and is_test_active() for skipped test>");
238 starttest(5, "SkipTest", pltbv, pltbs);
240 if (is_test_active(pltbv)) then
241 v_expected_tests_cnt := v_expected_tests_cnt + 1;
242 wait until rising_edge(clk);
244 report "Executing test that should have been skipped"
248 v_expected_skiptests_cnt := v_expected_skiptests_cnt + 1;
251 endtest(pltbv, pltbs);
252 print("<Done testing starttest() and is_test_active() for skipped test>");
254 print(lf & "<Testing waitclks()>");
256 wait until rising_edge(clk);
258 wait until rising_edge(clk);
261 report "clk_cnt after waitclks() incorrect:" & integer'image(clk_cnt) &
262 " expected:" & integer'image(10)
264 print("<Done testing waitclks()>");
266 print(lf & "<Testing check() integer>");
268 wait until rising_edge(clk);
269 check("Testing correct integer = 0", s_i, 0, pltbv, pltbs);
272 wait until rising_edge(clk);
273 check("Testing correct integer = 1", s_i, 1, pltbv, pltbs);
276 wait until rising_edge(clk);
277 check("Testing incorrect integer = 17", s_i, 18, pltbv, pltbs);
280 wait until rising_edge(clk);
281 check("Testing negative integer = -1", s_i, -1, pltbv, pltbs);
283 print("<Done testing check() integer>");
285 print(lf & "<Testing check() std_logic>");
287 wait until rising_edge(clk);
288 check("Testing correct std_logic = '0'", s_sl, '0', pltbv, pltbs);
291 wait until rising_edge(clk);
292 check("Testing correct std_logic = '1'", s_sl, '1', pltbv, pltbs);
295 wait until rising_edge(clk);
296 check("Testing incorrect std_logic = '1'", s_sl, '1', pltbv, pltbs);
298 print("<Done testing check() std_logic>");
300 print(lf & "<Testing check() std_logic against integer>");
302 wait until rising_edge(clk);
303 check("Testing correct std_logic = '0'", s_sl, 0, pltbv, pltbs);
306 wait until rising_edge(clk);
307 check("Testing correct std_logic = '1'", s_sl, 1, pltbv, pltbs);
310 wait until rising_edge(clk);
311 check("Testing incorrect std_logic = '1'", s_sl, 1, pltbv, pltbs);
314 wait until rising_edge(clk);
315 check("Testing std_logic = '1' with incorrect expected", s_sl, 2, pltbv, pltbs);
317 print("<Done testing check() std_logic against integer>");
319 print(lf & "<Testing check() std_logic_vector>");
321 wait until rising_edge(clk);
322 check("Testing correct std_logic_vector = x'00'", s_slv, x"00", pltbv, pltbs);
325 wait until rising_edge(clk);
326 check("Testing correct std_logic_vector = x'47'", s_slv, x"47", pltbv, pltbs);
329 wait until rising_edge(clk);
330 check("Testing incorrect std_logic_vector = x'11'", s_slv, x"10", pltbv, pltbs);
332 print("<Done testing check() std_logic_vector>");
334 print(lf & "<Testing check() std_logic_vector with mask>");
336 wait until rising_edge(clk);
337 check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, x"57", x"0F", pltbv, pltbs);
340 wait until rising_edge(clk);
341 check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, x"57", x"F0", pltbv, pltbs);
343 print("<Done testing check() std_logic_vector with mask>");
345 print(lf & "<Testing check() std_logic_vector against integer>");
347 wait until rising_edge(clk);
348 check("Testing correct std_logic_vector = x'00'", s_slv, 0, pltbv, pltbs);
351 wait until rising_edge(clk);
352 check("Testing correct std_logic_vector = x'47'", s_slv, 16#47#, pltbv, pltbs);
355 wait until rising_edge(clk);
356 check("Testing incorrect std_logic_vector = x'11'", s_slv, 16#10#, pltbv, pltbs);
359 wait until rising_edge(clk);
360 check("Testing negative std_logic_vector = x'FF'", s_slv, -1, pltbv, pltbs);
362 print("<Done testing check() std_logic_vector against integer>");
364 print(lf & "<Testing check() std_logic_vector with mask against integer>");
366 wait until rising_edge(clk);
367 check("Testing std_logic_vector = x'47' with correct nibble mask", s_slv, 16#57#, x"0F", pltbv, pltbs);
370 wait until rising_edge(clk);
371 check("Testing std_logic_vector = x'47' with incorrect nibble mask", s_slv, 16#57#, x"F0", pltbv, pltbs);
373 print("<Done testing check() std_logic_vector with mask against integer>");
375 print(lf & "<Testing check() unsigned>");
377 wait until rising_edge(clk);
378 check("Testing correct unsigned = x'00'", s_u, x"00", pltbv, pltbs);
381 wait until rising_edge(clk);
382 check("Testing correct unsigned = x'47'", s_u, x"47", pltbv, pltbs);
385 wait until rising_edge(clk);
386 check("Testing incorrect unsigned = x'11'", s_u, x"10", pltbv, pltbs);
388 print("<Done testing check() unsigned>");
390 print(lf & "<Testing check() unsigned against integer>");
392 wait until rising_edge(clk);
393 check("Testing correct unsigned = x'00'", s_u, 0, pltbv, pltbs);
396 wait until rising_edge(clk);
397 check("Testing correct unsigned = x'47'", s_u, 16#47#, pltbv, pltbs);
400 wait until rising_edge(clk);
401 check("Testing incorrect unsigned = x'11'", s_u, 16#10#, pltbv, pltbs);
403 print("<Done testing check() unsigned against integer>");
405 print(lf & "<Testing check() signed>");
407 wait until rising_edge(clk);
408 check("Testing correct signed = x'00'", s_s, x"00", pltbv, pltbs);
411 wait until rising_edge(clk);
412 check("Testing correct signed = x'47'", s_s, x"47", pltbv, pltbs);
415 wait until rising_edge(clk);
416 check("Testing incorrect signed = x'11'", s_s, x"10", pltbv, pltbs);
419 wait until rising_edge(clk);
420 check("Testing negative signed = x'FF'", s_s, x"FF", pltbv, pltbs);
422 print("<Done testing check() signed>");
424 print(lf & "<Testing check() signed against integer>");
426 wait until rising_edge(clk);
427 check("Testing correct signed = x'00'", s_s, 0, pltbv, pltbs);
430 wait until rising_edge(clk);
431 check("Testing correct signed = x'47'", s_s, 16#47#, pltbv, pltbs);
434 wait until rising_edge(clk);
435 check("Testing incorrect signed = x'11'", s_s, 16#10#, pltbv, pltbs);
438 wait until rising_edge(clk);
439 print("NOTE: Skipping test with negative signed. There seem to be a bug in ModelSim.");
445 print("<Done testing check() signed against integer>");
447 print(lf & "<Testing check() boolean>");
449 wait until rising_edge(clk);
450 check("Testing correct boolean = false", s_b, false, pltbv, pltbs);
453 wait until rising_edge(clk);
454 check("Testing correct boolean = true", s_b, true, pltbv, pltbs);
457 wait until rising_edge(clk);
458 check("Testing incorrect boolean = true", s_b, true, pltbv, pltbs);
460 print("<Done testing check() boolean>");
462 print(lf & "<Testing check() boolean against integer>");
464 wait until rising_edge(clk);
465 check("Testing correct boolean = false", s_b, 0, pltbv, pltbs);
468 wait until rising_edge(clk);
469 check("Testing correct boolean = true", s_b, 1, pltbv, pltbs);
472 wait until rising_edge(clk);
473 check("Testing incorrect boolean = true", s_b, 1, pltbv, pltbs);
476 wait until rising_edge(clk);
477 check("Testing boolean = true with incorrect expected", s_b, 2, pltbv, pltbs);
479 print("<Done testing check() boolean against integer>");
481 print(lf & "<Testing check() time>");
483 wait until rising_edge(clk);
484 check("Testing correct time = 0 sec", s_time, 0 sec, pltbv, pltbs);
487 wait until rising_edge(clk);
488 check("Testing correct time = 47 ns", s_time, 47 ns, pltbv, pltbs);
491 wait until rising_edge(clk);
492 check("Testing incorrect time = 10 us", s_time, 10 us, pltbv, pltbs);
494 print("<Done testing check() time>");
496 print(lf & "<Testing check() time with tolerance>");
498 wait until rising_edge(clk);
499 check("Testing correct unsigned = 0 sec +/- 0 sec", s_time, 0 sec, 0 sec, pltbv, pltbs);
502 wait until rising_edge(clk);
503 check("Testing correct time = 47 ns +/- 5 ns", s_time, 47 ns, 5 ns, pltbv, pltbs);
506 wait until rising_edge(clk);
507 check("Testing incorrect time = 10 us +/- 5 us", s_time, 10 us, 5 us, pltbv, pltbs);
509 print("<Done testing check() time with tolerance>");
511 print(lf & "<Testing check() string>");
512 s_str_exp <= string'("The quick brown fox jumps over the lazy dog.");
513 s_str1 <= string'("The quick brown fox jumps over the lazy dog.");
514 s_str2 <= string'("The quick brown dog jumps over the lazy fox.");
515 s_str3 <= string'("The quick brown fox jumps over the lazy dog");
516 s_str4 <= string'("The quick brown fox jumps over the lazy dog..");
517 wait until rising_edge(clk);
521 wait until rising_edge(clk);
525 wait until rising_edge(clk);
528 wait until rising_edge(clk);
531 print("<Done testing check() string>");
533 print(lf & "<Testing check() boolean expression>");
535 wait until rising_edge(clk);
536 check("Testing correct boolean expression 0 = 16#00#", s_i = 16#00#, pltbv, pltbs);
539 wait until rising_edge(clk);
540 check("Testing incorrect boolean expression 47 < 16#10#", s_i < 16#10#, pltbv, pltbs);
542 print("<Done testing check() boolean expresson>");
544 print(lf & "<Test readline() behaviour of the current simulator>");
545 print("Some simulators seem to handle CR and LF differently from others.");
547 print("DEBUG: file_open_status: " & file_open_status'image(f_status));
548 if f_status /= open_ok then
551 while not endfile(txtfile) loop
552 readline(txtfile, l);
553 line_num := line_num + 1;
554 write(msg, "Line " & str(line_num) & ": " & str(l'length) & " characters: ");
555 for i in l'range loop
556 write(msg, character'pos(l(i)));
557 write(msg, string'(" "));
559 writeline(output, msg);
562 print("<Done testing readline() behaviour>");
564 print(lf & "<Test reading binary files>");
569 print("DEBUG: file_open_status: " & file_open_status'image(f_status));
572 if f_status = open_ok then
575 while not endfile(binfile) loop
577 v_actual_data := character'pos(c);
583 if v_actual_data /= v_expected_data then
584 v_errcnt := v_errcnt + 1;
585 print("Error at offset " & str(i) & ": actual " & str(v_actual_data) & " expected " & str(v_expected_data));
590 check("Number of errors while reading binary file", v_errcnt, 0, pltbv, pltbs);
595 print("<Done testing reading binary files>");
597 print(lf & "<Testing check_binfile()");
606 print("<Done testing check_binfile()");
608 print(lf & "<Testing check_txtfile()");
617 print("<Done testing check_txtfile()");
619 print(lf & "<Testing check_datfile()");
628 print("<Done testing check_datfile()");
630 print(lf & "<Testing endtest()>");
631 endtest(pltbv, pltbs);
632 print("<Done testing endtest()>");
634 wait until rising_edge(clk);
635 print(lf & "<Testing endsim()>");
637 print("Expected number of tests: " & str(v_expected_tests_cnt));
638 print("Expected number of skipped tests: " & str(v_expected_skiptests_cnt));
639 print("Expected number of checks: " & str(v_expected_checks_cnt));
640 print("Expected number of errors: " & str(v_expected_errors_cnt));
641 if v_expected_errors_cnt = 0 then
642 print("Expected result: SUCCESS");
644 print("Expected result: FAIL");
646 wait until rising_edge(clk);
647 endsim(pltbv, pltbs, true);
648 wait until rising_edge(clk);
649 print("<Done testing endsim()>");
655 end architecture bhv;
Creates a clock for use in a testbench.
out clk_o std_logic
Clock output.
in stop_sim_i std_logic
Stops the clock when '1'.
G_PERIOD time := 10 ns
Clock period.
See pltbutils_comp.vhd for a description of the components.
This package defines fuctions and procedures for controlling stimuli to a DUT and checking response.
unsigned( 7 downto 0) s_u
boolean := false C_EXPECTED_SUCCESS
boolean := true C_EXPECTED_FAIL
pltbutils_clkgen clkgen0clkgen0
integer := 0 expected_checks_cnt
unsigned( 7 downto 0) s_s
check_cntC_EXPECT_FAIL,v_checks_cnt,v_errors_cnt,checks_cnt,errors_cnt,
string( 1 to 44) s_str_exp
pltbs_t := C_PLTBS_INIT pltbs
boolean := false clk_cnt_clr
std_logic_vector( 7 downto 0) s_slv
integer := 0 expected_errors_cnt
G_SKIPTESTS std_logic_vector :=( '0', '0', '0', '0', '0', '1')
G_BINTESTFILE_LONGER string := "../../../bench/testfiles/bintestfile_longer.txt"
G_TEXTTESTFILE_REFERENCE string := "../../../bench/testfiles/texttestfile_reference.txt"
G_DATTESTFILE_LONGER string := "../../../bench/testfiles/dattestfile_longer.dat"
G_TEXTTESTFILE_ERROR string := "../../../bench/testfiles/texttestfile_error.txt"
G_BINTESTFILE_LEN integer := 528
G_CLK_PERIOD time := 10 ns
G_BINTESTFILE_ERROR string := "../../../bench/testfiles/bintestfile_error.bin"
G_CHECKFILE_VERBOSITY integer := 10
G_BINTESTFILE_REFERENCE string := "../../../bench/testfiles/bintestfile_reference.bin"
G_TEXTTESTFILE_SHORTER string := "../../../bench/testfiles/texttestfile_shorter.txt"
G_TEXTTESTFILE_LONGER string := "../../../bench/testfiles/texttestfile_longer.txt"
G_DATTESTFILE_SHORTER string := "../../../bench/testfiles/dattestfile_shorter.dat"
G_DATTESTFILE_ERROR string := "../../../bench/testfiles/dattestfile_error.dat"
G_DATTESTFILE_REFERENCE string := "../../../bench/testfiles/dattestfile_reference.dat"
G_BINTESTFILE_CORRECT string := "../../../bench/testfiles/bintestfile_correct.bin"
G_TEXTTESTFILE_CORRECT string := "../../../bench/testfiles/texttestfile_correct.txt"
G_BINTESTFILE_SHORTER string := "../../../bench/testfiles/bintestfile_shorter.bin"
G_DATTESTFILE_CORRECT string := "../../../bench/testfiles/dattestfile_correct.dat"
G_BINTESTFILE_HEADER string := "Bintestfile R "
Defines useful functions an procedures for text handling text in VHDL.