pltbutils_comp_pkg.vhd

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library ieee;
  use ieee.std_logic_1164.all;
 
 
package pltbutils_comp_pkg is
 
  component pltbutils_clkgen is
    generic (
      G_PERIOD    : time := 10 ns;
      G_INITVALUE : std_logic := '0'
    );
    port (
      clk_o      : out   std_logic;
      clk_n_o    : out   std_logic;
      stop_sim_i : in    std_logic
    );
  end component pltbutils_clkgen;
 
  component pltbutils_time_measure is
    generic (
      G_VERBOSITY     : integer := 0;
      G_RPT_LABEL     : string  := "pltbutils_time_measure"
    );
    port (
      t_hi_o          : out time;             -- High time
      t_lo_o          : out time;             -- Low time
      t_per_o         : out time;             -- Period time
      s_i             : in  std_logic         -- Signal to measure
    );
  end component pltbutils_time_measure;
 
  component pltbutils_diff_check is
    generic (
      G_VERBOSITY     : integer := 0;
      G_RPT_LABEL     : string  := "pltbutils_diff_check"
    );
    port (
      diff_error_o    : out std_logic;        -- High when diff error detected
      diff_errors_o   : out integer;          -- Number of diff errors detected
      s_i             : in  std_logic;        -- Pos half of diff pair to check
      s_n_i           : in  std_logic := '0'; -- Neg half of diff pair to check
      rst_errors_i    : in  std_logic := '0'  -- High resets diff error counter
    );
  end component pltbutils_diff_check;
 
end package pltbutils_comp_pkg;