pltbutils_clkgen Entity Reference

Creates a clock for use in a testbench. More...

Inheritance diagram for pltbutils_clkgen:

Entities
bhv	architecture

Generics
G_PERIOD	time := 10 ns
	Clock period.
G_INITVALUE	std_logic := ' 0 '
	Initial value of the clock.

Ports
clk_o	out	std_logic
		Clock output.
clk_n_o	out	std_logic
		Inverted clock for differential clocks.
stop_sim_i	in	std_logic
		Stops the clock when '1'.

Detailed Description

Creates a clock for use in a testbench.

A non-inverted as well as an inverted output is available, use one or both depending on if you need a single-ended or differential clock. The clock stops when input port stop_sim goes '1'. This makes the simulator stop (unless there are other infinite processes running in the simulation).

Instantiation template

(copy to your own file and remove the comment characters):

pltbutils_clkgen0 : pltbutils_clkgen
 generic map (
   G_PERIOD        => G_PERIOD,
   G_INITVALUE     => '0'
 )
 port map (
   clk_o           => clk,
   clk_n_o         => clk_n,
   stop_sim_i      => stop_sim
 );

Definition at line 62 of file pltbutils_comp.vhd.

Member Data Documentation

clk_n_o

clk_n_o out std_logic

Port

Inverted clock for differential clocks.

Definition at line 69 of file pltbutils_comp.vhd.

clk_o

clk_o out std_logic

Port

Clock output.

Definition at line 68 of file pltbutils_comp.vhd.

G_INITVALUE

G_INITVALUE std_logic := ' 0 '

Generic

Initial value of the clock.

Definition at line 66 of file pltbutils_comp.vhd.

G_PERIOD

G_PERIOD time := 10 ns

Generic

Clock period.

Definition at line 64 of file pltbutils_comp.vhd.

stop_sim_i

stop_sim_i in std_logic

Port

Stops the clock when '1'.

Definition at line 71 of file pltbutils_comp.vhd.

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The documentation for this class was generated from the following file:

• src/vhdl/pltbutils_comp.vhd