bhv Architecture Reference

Processes
p_tc1
	Testcase process.

Signals
pltbs	pltbs_t := C_PLTBS_INIT
clk	std_logic
rst	std_logic
carry_in	std_logic
x	std_logic_vector ( G_WIDTH - 1 downto 0 )
y	std_logic_vector ( G_WIDTH - 1 downto 0 )
sum	std_logic_vector ( G_WIDTH - 1 downto 0 )
carry_out	std_logic

Instantiations
dut0	dut_example <Entity dut_example>
clkgen0	pltbutils_clkgen <Entity pltbutils_clkgen>

Detailed Description

Definition at line 53 of file tb_example1.vhd.

Member Function Documentation

p_tc1()

p_tc1

Testcase process.

Note

The purpose of the following code is to demonstrate some of the features of PlTbUtils, not to do a thorough verification.

Definition at line 98 of file tb_example1.vhd.

Member Data Documentation

carry_in

carry_in std_logic

Signal

Definition at line 62 of file tb_example1.vhd.

carry_out

carry_out std_logic

Signal

Definition at line 66 of file tb_example1.vhd.

clk

clk std_logic

Signal

Definition at line 60 of file tb_example1.vhd.

clkgen0

clkgen0 pltbutils_clkgen

Instantiation

Definition at line 92 of file tb_example1.vhd.

dut0

dut0 dut_example

Instantiation

Definition at line 83 of file tb_example1.vhd.

pltbs

pltbs pltbs_t := C_PLTBS_INIT

Signal

Simulation status- and control signals for accessing .stop_sim and for viewing in waveform window

Definition at line 57 of file tb_example1.vhd.

rst

rst std_logic

Signal

Definition at line 61 of file tb_example1.vhd.

sum

sum std_logic_vector ( G_WIDTH - 1 downto 0 )

Signal

Definition at line 65 of file tb_example1.vhd.

x

x std_logic_vector ( G_WIDTH - 1 downto 0 )

Signal

Definition at line 63 of file tb_example1.vhd.

y

y std_logic_vector ( G_WIDTH - 1 downto 0 )

Signal

Definition at line 64 of file tb_example1.vhd.

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The documentation for this class was generated from the following file:

• examples/vhdl/tb_example1/tb_example1.vhd