PlTbUtils  1.3
PlTbUtils is a collection of functions, procedures and components for easily creating stimuli and checking response in automatic self-checking testbenches.
Generics | Ports
dut_example Entity Reference
Inheritance diagram for dut_example:

Entities

rtl  architecture
 

Generics

G_WIDTH  integer := 8
G_DISABLE_BUGS  integer range 0 to 1 := 1

Ports

clk_i   in   std_logic
rst_i   in   std_logic
carry_i   in   std_logic
x_i   in   std_logic_vector ( G_WIDTH - 1 downto 0 )
y_i   in   std_logic_vector ( G_WIDTH - 1 downto 0 )
sum_o   out   std_logic_vector ( G_WIDTH - 1 downto 0 )
carry_o   out   std_logic

Detailed Description

Definition at line 43 of file dut_example.vhd.

Member Data Documentation

◆ carry_i

carry_i in std_logic
Port

Definition at line 51 of file dut_example.vhd.

◆ carry_o

carry_o out std_logic
Port

Definition at line 56 of file dut_example.vhd.

◆ clk_i

clk_i in std_logic
Port

Definition at line 49 of file dut_example.vhd.

◆ G_DISABLE_BUGS

G_DISABLE_BUGS integer range 0 to 1 := 1
Generic

Definition at line 47 of file dut_example.vhd.

◆ G_WIDTH

G_WIDTH integer := 8
Generic

Definition at line 45 of file dut_example.vhd.

◆ rst_i

rst_i in std_logic
Port

Definition at line 50 of file dut_example.vhd.

◆ sum_o

sum_o out std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 54 of file dut_example.vhd.

◆ x_i

x_i in std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 52 of file dut_example.vhd.

◆ y_i

y_i in std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 53 of file dut_example.vhd.

The documentation for this class was generated from the following file: