PlTbUtils  1.3
PlTbUtils is a collection of functions, procedures and components for easily creating stimuli and checking response in automatic self-checking testbenches.
Generics | Ports
tc_example2 Entity Reference
Inheritance diagram for tc_example2:

Entities

tc1  architecture
 

Generics

G_WIDTH  integer := 8
G_DISABLE_BUGS  integer range 0 to 1 := 0

Ports

pltbs   out   pltbs_t
clk   in   std_logic
rst   out   std_logic
carry_in   out   std_logic
x   out   std_logic_vector ( G_WIDTH - 1 downto 0 )
y   out   std_logic_vector ( G_WIDTH - 1 downto 0 )
sum   in   std_logic_vector ( G_WIDTH - 1 downto 0 )
carry_out   in   std_logic

Detailed Description

Definition at line 41 of file tc_example2.vhd.

Member Data Documentation

◆ carry_in

carry_in out std_logic
Port

Definition at line 50 of file tc_example2.vhd.

◆ carry_out

carry_out in std_logic
Port

Definition at line 55 of file tc_example2.vhd.

◆ clk

clk in std_logic
Port

Definition at line 48 of file tc_example2.vhd.

◆ G_DISABLE_BUGS

G_DISABLE_BUGS integer range 0 to 1 := 0
Generic

Definition at line 45 of file tc_example2.vhd.

◆ G_WIDTH

G_WIDTH integer := 8
Generic

Definition at line 43 of file tc_example2.vhd.

◆ pltbs

pltbs out pltbs_t
Port

Definition at line 47 of file tc_example2.vhd.

◆ rst

rst out std_logic
Port

Definition at line 49 of file tc_example2.vhd.

◆ sum

sum in std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 53 of file tc_example2.vhd.

◆ x

x out std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 51 of file tc_example2.vhd.

◆ y

y out std_logic_vector ( G_WIDTH - 1 downto 0 )
Port

Definition at line 52 of file tc_example2.vhd.

The documentation for this class was generated from the following file: