Posts
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Where Can I Assert in VHDL?
After reading Stuart Sutherland’s paper “Who Put Assertions In My RTL Code? And Why? - How RTL Design Engineers Can Benefit from the Use of SystemVerilog Assertions”, I wondered where we can insert assertions in VHDL since the paper focuses on System Verilog.
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SW Test Methods in VHDL
When testing SW there are two methods that are primarily used to handle dependencies that are not needed for a test: stubbing and mocking. For embedded SW the dependencies are usually on HW or the MCU’s Hardware Abstraction Layer (HAL). For application SW the dependencies are usually one of these: the file system, the internet, or other applications. In short, these dependencies are usually removed and their interface is fulfilled by another, more effective and simpler mechanism. In VHDL the HW interface is nicely abstracted through ports and testbenches without ports are standard industry practice for simulating the effects of HW stimulus on a design. When dealing with the VHDL counterpart of a file system; memory access, mocking may speed up simulations by providing a memory model that is effective for simulations. Finally, VHDL also interfaces with other applications: processing units that either run SW (softcore-CPUs) or are designed to infer information about their inputs in a hard-to-predict manner; AI accelerators or Tensor Processing Units (TPUs). In this post I’ll mention stubbing briefly and then cover how to mock a processing unit in VHDL.
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VHDL Testbench Library Comparison
This post is an overview of testbench utility libraries, verification components will be covered in a separate post. The intention is to help with selecting which library to use, since I haven’t found a neutral comparison of them anywhere.
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VHDL Design Patterns: Test Controller
Chapter 5 of OSVVM’s Test Writer’s User Guide explains how their testbench framework consists of a test sequencer, TestCtrl, and a top level testbench which they call a test harness. However, no examples are given on how to create this setup. I resorted to digging around in OSVVM’s own testbenches to find out how to do that. This post will cover how to create your own setup of the testbench framework with a test controller.
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VUnit
VUnit “features the functionality needed to realize continuous and automated testing” of HDL code. It takes care of building, running tests (via a simulator like GHDL) and evaluating the results. It also offers VHDL convenience procedures, functions and components as well as Verification Components. This post will cover the build/run functionality, the convenience library will be covered in a separate post.
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GHDL
GHDL is “a VHDL analyzer, compiler, simulator and (experimental) synthesizer that can process (nearly) any VHDL design.”
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Doxygen for VHDL
Doxygen is the industry standard in SW development for auto-generating documentation from code. It works pretty well for VHDL, I’ll cover the basics, share some tips and tricks and provide a few warnings in this post.
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VHDL Style Guide (VSG)
VHDL Style Guide describes it self as a tool that “provides coding style guide enforcement for VHDL code”. It is similar to clang-tidy or Black in that it can fix your code to follow a coding styleguide. This post is a quick overview of VSG to help you get started using it.